Tuesday, January 17, 2012

Publication 2

My second publication was published in November. (See here for my first one.) I am the primary author on this paper:

Applied Physics Express, 4(11), 114101

Enhancement-Mode Insulating-Gate AlInN/AlN/GaN Heterostructure Field-Effect Transistors with Threshold Voltage in Excess of +1.5 V
Daniel Morgan, Mahbuba Sultana1, Husna Fatima, Sho Sugiyama1, Qhalid Fareed, Vinod Adivarahan, Mohamed Lachab1, and Asif Khan1
Nitek Inc., Salem Church Road, Irmo, SC 29063, U.S.A.
1Department of Electrical Engineering, University of South Carolina, Columbia, SC 29208, U.S.A.


This letter presents the dc characteristics of normally Off AlInN/AlN/GaN metal–oxide–semiconductor heterostructure field-effect transistors (MOS-HFETs). The devices were fabricated using a recessed gate and SiON dielectric layers for gate isolation. For a device with a 1.5 µm gate length and an 8-µm-long channel, the threshold voltage was above +1.5 V and a maximum drain current density of 0.7 A/mm was reached under 6 V gate bias. These enhancement-mode MOS-HFETs have an excellent potential for power electronics applications. ©2011 The Japan Society of Applied Physics
(Received August 26, 2011; accepted September 23, 2011; published online October 18, 2011)